Next-generation integrated RF transceivers are required to support up to 1024-QAM in the down-link. To meet the stringent error vector magnitude (EVM) requirements for such high modulation orders, the digital phase locked loop (DPLL) generating the local oscillator (LO) signal has to have very low integrated phase noise. The phase noise can be significantly improved by running the DPLL at a high reference clock frequency. This reduces the time-to-digital converter (TDC) noise caused by quantization, nonlinearity (DNL/INL) and analog delay jitter.